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RTL Simulation and Synthesis with PLDs (18PC5701

COURSE: M.TECH(VLSID)                                                BRANCH:  ECE

YEAR & SEM:   I-I                                                                 REGULATION: R18

UNIT- I

PART-A
1) a) Explain the Top-down Design process with neat sketch.
b) Give the differences between Mealy and Moore FSM with examples.
2) Explain the following terms
a) Classifier
b) Acceptor
c) Transducer
d) Sequencer
3) a) Define the states of FSM and draw the state diagram.
b) Explain the behavioural model of Finite State Machines.
4) a) With the aid of the necessary state diagram and the relevant state table, explain the one-hot design method for state machine design.
b) Discuss about Synthesis of finite state machines.
5) a) With suitable example, explain the top down design approach for FPGAs using Finite state machines.
b) How Meta Stability can be avoided in finite state machines?
PART-B
6) a) Explain the data path and functional partition of FSM system level design.
b) Explain the derivations of state machine changes.
7) Write short notes on i) Static Timing Analysis
ii) Meta Stability
8) a) Explain the rules for clocking for clocking in FSM design.
b) Explain about Clock Skew and Clock Jitter.
9) a) Write short notes on clocking discipline.
b) Explain about Delay Modelling
10) a) Briefly explain the need and design strategies for multi-clock domain designs.
b) Explain about the term ‘synchronization’. Give its significance.

UNIT-II

PART-A
1. a) Discuss various descriptive styles available for hardware modelling using VHDL.
b) Briefly explain Top Down design and Bottom Up implementations in VHDL.
2. Explain the terms
i) Design Entry
ii) Optimization relevant to VHDL.
3. a) List the VHDL operators and explain function of each one with examples.
b) Give the behavioural description of MSI based hardware in VHDL. Draw the logic diagram.
4. a) Write objects and classes in a VHDL.
b) How signal assignments can do in the VHDL.
5) a) Write VHDL code for 2-bit synchronous counter.
b) Explain the differences between VHDL and Verilog HDL.

PART-B

6) a) Explain behavioural description in Verilog.
b) Explain conditional operator, operator precedence in VERILOG.
7) Write the syntax for following statements:
a) process
b) case
c) wait
d) loop
8) Explain following concepts with examples:
a) Verilog Strings
b) Verilog Constants
c) Verilog Operations.
d) Verilog Variables.
9) a) Differentiate the combinational and sequential behaviour of user-defined primitives for hardware modelling using Verilog HDL.
b) Explain the structural design methodology with the verilog HDL.
10) a) Explain the need of designing FSM.
b) Explain the features of state machine designs centred around shift registers.

UNIT-III

PART-A
1. a) Compare ROM, PAL, PLA and PLD.
b) Implement the following Boolean function using a suitable PAL.
F(a, b, c, d) = Σ m (2, 4, 6, 8, 10, 11, 12, 14, 15).
2. a) Define the term `programmable logic device’. Draw the basic configurations of PLDs and give their features and applications.
b) Write short notes on System-on-Chip(SoC)
3. a) Explain about the FPGA architecture with block diagram.
b) Explain the physical design cycle of FPGA.
4. a) With diagram explain FUSE and ANTIFUSE mechanism of FPGA programming.
b) Give the differences between FPGA’s and CPLD’s.
5. a) Draw and explain logic blocks of FPGA.
b) Explain FPGA design flow and compare FPGA design flow with ASIC design flow.
6. a) Draw and explain the routing architecture of field programmable gate arrays.
b) Discuss in brief, the following relevant to field programmable gate arrays.
i. Design flow
ii. Technology mapping.
PART-B
7) Explain the following
i) Floor planning methods
ii) Placement and Routing
8) a) Explain the routing problems in floor planning methods of VLSI design.
b) How partitioning is performed for segmented & staggered model.
9) a) Explain with an algorithm how routing problems can be overcome?
b) With the help of a neat sketch explain the principle and working of topological routing.
10)Write short notes on the following
a) Multiple Stage routing
b) Maze routing
c) Area routing
d) Channel routing
11)a) Explain any one partitioning method in detail.
b) Differentiate global routing and detailed routing.
12) a) Discuss about the goals and objectives of Floor planning in detail.
b) Explain the following
i) Power analysis
ii) ESD protection

UNIT-IV

PART-A
1) a) What are the implications of low power design of IC fabrication? Explain.
b) Give the overview of low power VLSI design with neat sketch.
2) a) Compare low power VLSI design techniques with conventional design methods.Department of Electronics and Communication Engineering
b) Write about low power techniques for SRAM.
3) a) Explain the design approach for low power Flip Flops.
b) What are the advantages of Scaling in Low power VLSI Design? Explain.
4) a) What are the different technical parameter issues connected with VLSI Low Power, Low voltage design? Explain.
b) Explain about SOI technology and indicate how this technology helps in Low Power Design.
PART-B
5) a) Explain any two BIST concepts.
b) Explain board level & system level DFT approaches.
6) a) List and explain memory test requirements for MBIST.
b) Explain about Adhoc design for testability techniques.
7) Explain the following
(a) Pseudorandom testing
(b) Pseudo exhaustive testing
8) a) Draw the block diagram for a BIST implementation using BIBO and explain the test procedure.
b) Explain the counter test technique for RAM BIST.
9) a) Write a note on ad hoc DFT methods.
b) How a mutual comparator useful for memory BIST? Explain.
10) a) With a block diagram, explain full circular BIST configuration.
b) Differentiate between genetic boundary scan and full integrated scan.
11) a) With the help of neat block diagram, explain the scan Architectures & Testing.
b) Explain any Two BIST architectures.
i) CSBL
ii) LOCST
iii) RTD

12) Write short notes on the following:
a) Full Integrated Scan
b) CSTP- BIST architecture

UNIT-V

1) a) Discuss about prototyping use models.
b) Discuss about user priorities in prototyping.
2) a) Explain about FPGA based prototyping for different aims.
b) Give the prototyping power saving features.
3) a) Give the overview of FPGA based prototyping process.
b) Discuss about the implementation tools needed during prototyping.
4) Discuss about IP in different forms.
5) Explain the following:
a) Soft IP
b) Peripheral IP
6) Write a short note on the following:
a) Net list
b) Use of external hard IP during prototype
c) Benefits of portable prototype