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CAD (18PE5703)

COURSE: M.TECH(VLSID)                                                BRANCH:  ECE

YEAR & SEM:   I-I                                                                 REGULATION: R18

UNIT-I

Part-I
1. (a). With neat flow graph explain the steps in VLSI design cycle.
(b). What are the new trends in VLSI design cycle? Explain in detail.
2. (a). Explain the steps in Physical design cycle with neat diagram.
(b). Discuss about the new trends in Physical design cycle.
3. (a). Describe the Various design style in VLSI design.
(b). Compare different Design Styles in VLSI design
5. (a). What are the different Packaging Styles? Explain each one in detail.
(b). Compare Different Packaging Styles.
Part-II
6. (a). Differentiate Full custom design and Semi custom design.
(b). Explain about Standard Cell Design
7. (a). What is Gate Array? Explain. Extend the Discussion to Field Programmable Gate Array.
(b). Compare different Design Styles in VLSI design
8. (a). Discuss about Die packaging and attachment styles.
(b). Explain in detail about Printed Circuit Boards
9. (a). Explain in detail about Multi Chip Module.
(b). Explain in detail about Wafer Scale Integration.

UNIT-II

Part-I
1. What are the different levels of Partitioning? Explain in detail
2. List the Parameters that Deals with Partitioning Problem. Explain each in detail.
3. What are the different design style specific partitioning problems? Explain each in detail.
4. (a). Explain about Kernighan-Lin algorithm.
(b). What are the extensions that can be proposed to Kernighan-Lin Algorithm? Explain?
Part-II
5. (a). What is Simulated Annealing? Explain?
(b). What is Simulated Evolution? Explain?
6. Explain about Metric allocation method.
7. Discuss about Performance Driven Partitioning.

UNIT-III

Part-I

1. What is Floorplanning? Explain in detail.
2. Mention different Floorplanning algorithms and explain each in detail.
3. What is Pin Assignment? Explain in detail.4. Mention different Pin Assignment algorithms and explain each in detail.
Part-II
5. (a). Explain in detail about constraint based Floorplanning.
(b). Discuss about Integer Programming based Floorplanning.
6. (a). Explain in detail about Rectangular Dualization.
(b). What is Timing Driven Foorplanning? Explain
7. (a). Explain about General Pin Assignment algorithm.
(b). Discuss about Channel Pin Assignment algorithm.

UNIT-IV

Part-I
1. (a). What are the three levels of Placement Blocks
(b). Explain about Design Style Specific Placement Problems
2. What are the different Placement Problems
3. Explain in detail about Partitioning based Placement Algorithms
4. (a). Draw the Two phase Routing Flow graph and explain
(b). Explain the different Global Routing Problems
5. What are the design style specific Global Routing Problems? Explain in detail.
Part-II
6. (a). What are the different Global Routing Algorithms? Explain in detail.
(b). Explain about Maze Routing Algorithms
7. (a). What are the different Routing considerations for Detailed Routing?
(b). Explain about different Routing Models.
8. (a). Discuss about Channel Routing Problems in detail.
(b). Explain about Switch box Routing Problems.
9. (a). Explain about Design style specific Detailed Routing Problems
(b). Explain the classifications of Detailed Routing Algorithms.
10. Explain in detail about Single Layer Routing Algorithms.

UNIT-V

Part-I
1. Discuss different FPGA technologies in detail.
2. (a). Explain about FPGA physical design cycle.
(b). Discuss different Routing algorithms for FPGA
Part-II
1. (a). What is MCM? Explain about different MCM technologies.
(b). Explain about MCM physical design cycle.
2. Explain the Routing Algorithms for Segmented and Non Segmented Model.